BLOCK DIAGRAM
clk
Opcode
decoder
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xramaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xramdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
I/O Port
registers
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
t0
t1
gate0
gate1
rxdi
rxdo
txd
int0
int1
int2
int3
int4
int5
int6
PINS DESCRIPTION
PIN
reset
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
iprgramsize[2:0]
iprgromsize[2:0]
prgramdata[7:0]
prgromdata[7:0]
sxdmdatai[7:0]
xdatai[7:0]
ready
ramdatai[7:0]
sfrdatai[7:0]
int0
int1
int2
int3
int4
int5
int6
t0
t1
t2
gate0
gate1
t2ex
capture0
capture1
capture2
capture3
rxd0o
rxd0i
txd0
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
DESCRIPTION
Global clock
Global reset
Port 0 input
Port 1 input
Port 2 input
Port 3 input
Size of on-chip RAM CODE
Size of on-chip ROM CODE
Data bus from int. RAM prog. memory
Data bus from int. ROM prog. memory
Data bus from sync external data
memory (SXDM)
Data bus from external memories
External memory data ready
Data bus from internal data memory
Data bus from user SFR’s
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Timer 0 input
Timer 1 input
Timer 2 input
Timer 0 gate input
Timer 1 gate input
Timer 2 gate input
Timer 2 capture 0 line
Timer 2 capture 1 line
Timer 2 capture 2 line
Timer 2 capture 3 line
Serial receiver input 0
Serial receiver input 1
Master/Slave I2C clock line input
Master/Slave I2C data input
SPI slave select
SPI slave input
SPI master input
SPI clock input
DoCD™ TAP data input
DoCD™ TAP clock input
DoCD™ TAP mode select input
Program
memory
interface
Timers
External
memory
interface
UART
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
Control
Unit
Interrupt
controller
Internal data
memory
interface
Power
Manage-
ment Unit
stop
pmm
User SFR’s
interface
DoCD™
Debug Unit
tdi
tck
tms
tdo
rtck
coderun
debugacs
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
Floating
Point Unit
SXDM
interface
t2
t2ex
Timer 2
Watchdog
Timer
Compare
Capture
UART 0
rxd1o
rxd1i
txd1
UART 1
capture0
capture1
capture2
capture3
rxdi0
rxdi1
scli
sdai
ss
si
mi
scki
tdi
tck
tms
rsto
port0o[7:0]
port1o[7:0]
port2o[7:0]
MDU32
SPI Unit
sclhs
scli
sclo
sdai
sdao
clk
reset
rsto
Master/
Slave I2C
Unit
ALU
so
si
mo
mi
scko
scki
scken
ss
sso(7:0)
soen
output Reset output
output Port 0 output
output Port 1 output
output Port 2 output
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are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
