●
Floating-Point math coprocessor - IEEE-
754 standard single precision real, word
and short integers
○
○
○
○
○
○
○
○
can be excluded from the core by changing
appropriate constants in package file.
FADD, FSUB- addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM- compare
FCHS - change sign
FABS - absolute value
FSIN, FCOS- sine, cosine
FTAN, FATAN- tangent, arcs tangent
DELIVERABLES
♦
Source code:
◊
VHDL Source Code or/and
◊
VERILOG Source Code or/and
◊
Encrypted, or plain text EDIF netlist
♦
VHDL & VERILOG test bench environment
◊
Active-HDL automatic simulation macros
◊
ModelSim automatic simulation macros
◊
Tests with reference responses
♦
Technical documentation
◊
Installation notes
◊
HDL core specification
◊
Datasheet
♦
Synthesis scripts
♦
Example application
♦
Technical support
◊
IP Core implementation support
◊
3 months maintenance
●
●
●
CONFIGURATION
The following parameters of the DP8051XP
core can be easy adjusted to requirements of
dedicated application and technology. Configu-
ration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
Internal Program Memory
type
- synchronous
- asynchronous
-
0 - 64kB
-
-
0 - 64kB
-
- true
- false
- used
- unused
- used
- unused
- used
- unused
- used
- unused
-
subroutines
location
Internal Program ROM
•
Memory size
•
•
•
Internal Program RAM
Memory size
Internal Program Memory
fixed size
Second Data Pointer
(DPTR1)
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design
license allows using IP Core in
single FPGA bitstream and ASIC implementa-
tion. It also permits FPGA prototyping before
ASIC production.
Unlimited Designs
license allows using IP Core
in unlimited number of FPGA bitstreams and
ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
Single Design license for
○
VHDL, Verilog source code called HDL Sour-
•
DPTR0 decrement
•
DPTR1 decrement
•
Data Pointers auto-switch
•
Interrupts
•
Timing access protection
•
Power Management Mode
•
Stop mode
•
DoCD™ debug unit
- used
- unused
- used
- unused
- used
- unused
- used
- unused
ce
○
Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○
HDL Source
○
Netlist
Besides mentioned above parameters all
available peripherals and external interrupts
All trademarks mentioned in this document
are trademarks of their respective owners.
●
Upgrade from
○
Netlist to HDL Source
○
Single Design to Unlimited Designs
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
