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Dedicated signal for Program Memory
writes.
Interface for additional Special Function
Registers
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
Scan test ready
2.0 GHz virtual
clock frequency in a 0.25u
technological process
●
Three 16-bit timer/counters
○
Timers clocked by internal source
○
Auto reload 8/16-bit timers
○
Externally gated event counters
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Full-duplex serial port
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Synchronous mode, fixed baud rate
8-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, variable baud rate
7-bit and 10-bit addressing modes
NORMAL, FAST, HIGH speeds
Multi-master systems supported
Clock arbitration and synchronization
User defined timings on I2C lines
Wide range of system clock frequencies
Interrupt generation
NORMAL speed 100 kbs
FAST speed 400 kbs
HIGH speed 3400 kbs
Wide range of system clock frequencies
User defined data setup time on I2C lines
Interrupt generation
●
I2C bus controller - Master
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PERIPHERALS
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DoCD™ debug unit
○
Processor execution control
Run
Halt
Step into instruction
Skip instruction
○
Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○
Code execution breakpoints
one real-time PC breakpoint
unlimited number of real-time OPCODE break-
points
○
Hardware execution watch-point
one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
○
Hardware watch-points activated at a certain
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
○
Unlimited number of software watch-points
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○
Unlimited number of software breakpoints
Program Memory(PC)
○
Automatic adjustment of debug data transfer
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I2C bus controller - Slave
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SPI – Master and Slave Serial Peripheral
Interface
○
Supports speeds up ¼ of system clock
Mode fault error
Write collision error
○
Four transfer formats supported
○
System errors detection
○
Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○
Interrupt generation
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Programmable Watchdog Timer
16-bit Compare/Capture Unit
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speed rate between HAD and Silicon
○
JTAG Communication interface
Events capturing
Pulses generation
Digital signals generation
Gated timers
Sophisticated comparator
Pulse width modulation
Pulse width measuring
Multiplication - 16bit
*
16bit
Multiplication - 32bit
*
32bit
Division - 32bit / 32bit
Division - 16bit / 16bit
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Power Management Unit
○
Power management mode
○
Switchback feature
○
Stop mode
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Fixed-Point arithmetic coprocessor
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Extended Interrupt Controller
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2 priority levels
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Up to 7 external interrupt sources
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Up to 8 interrupt sources from peripherals
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Floating-Point
arithmetic
coprocessor
IEEE-754 standard single precision
○
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Four 8-bit I/O Ports
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Bit addressable data direction for each line
○
Read/write of single line and 8-bit group
FADD, FSUB - addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM - compare
FCHS - change sign
FABS - absolute value
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http://www.dcd.pl
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are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
