computed as {80C51 clock periods} divided by
{DP8051CPU clock periods} required to exe-
cute an identical function. More details are
available in core documentation.
8
8
prgramdatai
prgdatao
On-chip Memory
(implemented as RAM)
0 Wait-State access
prgramwr
12
10
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
Improvement
9,00
prgaddr
On-chip Memory
(implemented as ROM)
0 Wait-State access
9,00
9,00
12,00
9,00
9,00
8
prgromdata
ASIC or FPGA
chip
DP8051CPU
xdatai
xdatao
xaddr
9,00
8
12,00
16,00
9,60
Off-chip Memory
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
16
8-bit division
xprgrd
xprgwr
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
12,00
12,00
13,60
12,00
12,00
12,60
Wait-States
manager
ready
Average speed improvement:
11,12
The described above implementation should be
treated as an example. All Program Memory
spaces are fully configurable. For timing-critical
applications whole program code can be imple-
mented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cy-
cles.
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DP8051CPU per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
Clock
Dhry/sec
(VAX MIPS)
Device
Target
fre-
quency
12 MHz
33 MHz
80C51
80C310
-
-
268 (0.153)
1550 (0.882)
DP8051CPU STRATIX-II 150 MHz 26220 (14.924)
Core performance in terms of Dhrystones
26220
27000
24000
21000
18000
15000
12000
9000
P E R F O R M A N C E
The following tables give a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (CPU fea-
tures and peripherals have been included):
Device
FLEX10KE
ACEX1K
APEX20K
APEX20KE
APEX20KC
APEX-II
MERCURY
CYCLONE
CYCLONE-II
STRATIX
Speed grade
Fmax
6000
1550
-1
-1
-1
-1
-7
-7
-5
-6
-6
-5
-3
57 MHz
56 MHz
50 MHz
68 MHz
79 MHz
74 MHz
101 MHz
93 MHz
95 MHz
89 MHz
160 MHz
268
3000
0
80C51 (12MHz)
80C310 (33MHz)
DP8051CPU (150MHz)
Area utilized by the each unit of DP8051CPU
core in vendor specific technologies is summa-
rized in table below.
STRATIX-II
Core performance in ALTERA® devices
Area
Component
[LC]
1640
100
10
[FFs]
285
40
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
CPU*
Interrupt Controller
Power Management Unit
5
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