rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
PIN
TYPE
DESCRIPTION
tms
rsto
input DoCD™ TAP mode select input
output Reset output
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
port0o[7:0]
port1o[7:0]
port2o[7:0]
port3o[7:0]
prgaddr[15:0]
prgdatao[7:0]
prgramwr
output Port 0 output
output Port 1 output
output Port 2 output
output Port 3 output
output Internal program memory address bus
output Data bus for internal program memory
output Internal program memory write
External Memory Interface - Contains mem-
ory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It per-
forms the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
sxdmaddr[15:0] output Sync XDATA memory address bus
(SXDM)
sxdmdatao[7:0] output Data bus for Sync XDATA memory
(SXDM)
sxdmoe
sxdmwe
xaddr[23:0]
xdatao[7:0]
xdataz
output Sync XDATA memory read (SXDM)
output Sync XDATA memory write (SXDM)
output Address bus for external memories
output Data bus for external memories
output Turn xdata bus into ‘Z’ state
output External program memory read
output External program memory write
output External data memory read
output External data memory write
output Internal Data Memory address bus
output Data bus for internal data memory
output Internal data memory output enable
output Internal data memory write enable
output Address bus for user SFR’s
output Data bus for user SFR’s
xprgrd
Synchronous
eXternal
Data
Memory
xprgwr
(SXDM) Interface – contains XDATA memory
access related logic allowing fast access to
synchronous memory devices. It performs the
external Data Memory addressing and data
transfers. This memory can be used to store
large variables frequently accessed by CPU,
improving overall performance of application.
xdatard
xdatawr
ramaddr[7:0]
ramdatao[7:0]
ramoe
ramwe
sfraddr[6:0]
sfrdatao[7:0]
sfroe
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo
output DoCD™ TAP data output
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
rtck
output DoCD™ return clock line
debugacs
coderun
pmm
output DoCD™ accessing data
output CPU is executing an instruction
output Power management mode indicator
output Stop mode indicator
stop
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
U N I T S S U M M A R Y
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Man-
agement Mode) to significantly reduce power
consumption. Switchback feature allows
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
