S Y M B O L
B L O C K D I A G R A M
prgromdata(7:0)
prgramdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
Opcode
decoder
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
Program
memory
interface
xdatai(7:0)
ready
xaddr(23:0)
xdatao(7:0)
xdataz
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
xaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xdataz
SXDM
interface
iprgromsize(2:0)
iprgramsize(2:0)
xprgrd
xprgwr
xdatard
xdatawr
External
memory
interface
sxdmwe
ready
xprgrd
xprgwr
xdatard
xdatawr
int0
int1
Interrupt
controller
sxdmxdatai(7:0)
sxdmadd(15:0)
sxdmdatao(7:0)
sxdmwe
Control
Unit
iprgromsize(2:0)
iprgramsize(2:0)
Power
Manage-
ment Unit
stop
sxdmoe
pmm
ramdatai(7:0)
sfrdatai(7:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramaddr(7:0)
ramdatao(7:0)
ramwe
Internal data
memory
interface
tdi
tck
tms
tdo
rtck
DoCD™
Debug Unit
ramoe
ramoe
coderun
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
debugacs
User SFR’s
interface
sfraddr(6:0)
sfrdatao(7:0)
sfroe
int0
int1
sfrwe
ALU
clk
reset
sfrwe
P I N S D E S C R I P T I O N
stop
pmm
PIN
TYPE
DESCRIPTION
clk
input Global clock
input Global reset
input Port 0 input
input Port 1 input
input Port 2 input
input Port 3 input
tdo
rtck
tdi
reset
tck
tms
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
coderun
debugacs
reset
clk
rsto
iprgramsize[2:0] input Size of on-chip RAM CODE
iprgromsize[2:0] input Size of on-chip ROM CODE
prgramdata[7:0] input Data bus from int. RAM prog. memory
prgromdata[7:0] input Data bus from int. ROM prog. memory
sxdmdatai[7:0]
input Data bus from sync external data
memory (SXDM)
xdatai[7:0]
ready
input Data bus from external memories
input External memory data ready
input Data bus from internal data memory
input Data bus from user SFR’s
input External interrupt 0
ramdatai[7:0]
sfrdatai[7:0]
int0
int1
input External interrupt 1
tdi
input DoCD™ TAP data input
input DoCD™ TAP clock input
tck
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
