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DP80390CPU 参数 Datasheet PDF下载

DP80390CPU图片预览
型号: DP80390CPU
PDF下载: 下载PDF文件 查看货源
内容描述: 流水线的高性能8位微控制器 [Pipelined High Performance 8-bit Microcontroller]
分类和应用: 微控制器
文件页数/大小: 10 页 / 210 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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spaces are fully configurable. For timing-critical  
applications whole program code can be imple-  
mented as on-chip ROM and (or) RAM and  
executed without Wait-States, but for some  
other applications whole program code can be  
implemented as off-chip ROM or FLASH and  
executed with required number Wait-State cy-  
cles.  
P E R F O R M A N C E  
The following tables give a survey about the  
Core area and performance in Programmable  
Logic Devices after Place & Route (CPU fea-  
tures and peripherals have been included):  
Device  
FLEX10KE  
ACEX1K  
APEX20K  
APEX20KE  
APEX20KC  
APEX-II  
MERCURY  
CYCLONE  
CYCLONE-II  
STRATIX  
Speed grade  
Fmax  
-1  
-1  
-1  
-1  
-7  
-7  
-5  
-6  
-6  
-5  
-3  
57 MHz  
56 MHz  
50 MHz  
63 MHz  
76 MHz  
74 MHz  
101 MHz  
93 MHz  
95 MHz  
98 MHz  
160 MHz  
STRATIX-II  
Core performance in ALTERA® devices  
For a user the most important is application  
speed improvement. The most commonly used  
arithmetic functions and theirs improvement  
are shown in table below. Improvement was  
computed as {80C51 clock periods} divided by  
{DP80390CPU clock periods} required to exe-  
cute an identical function. More details are  
available in core documentation.  
Function  
8-bit addition (immediate data)  
8-bit addition (direct addressing)  
8-bit addition (indirect addressing)  
8-bit addition (register addressing)  
8-bit subtraction (immediate data)  
8-bit subtraction (direct addressing)  
8-bit subtraction (indirect addressing)  
8-bit subtraction (register addressing)  
8-bit multiplication  
Improvement  
9,00  
9,00  
9,00  
12,00  
9,00  
9,00  
9,00  
12,00  
16,00  
9,60  
8-bit division  
16-bit addition  
16-bit subtraction  
16-bit multiplication  
32-bit addition  
32-bit subtraction  
32-bit multiplication  
12,00  
12,00  
13,60  
12,00  
12,00  
12,60  
Average speed improvement:  
11,12  
Dhrystone Benchmark Version 2.1 was used to  
measure Core performance. The following ta-  
ble gives a survey about the DP80390CPU  
performance in terms of Dhrystone/sec and  
VAX MIPS rating.  
Clock  
frequency  
12 MHz  
Dhry/sec  
Device  
80C51  
80C310  
Target  
(VAX MIPS)  
268 (0.153)  
1550 (0.882)  
-
-
33 MHz  
DP80390CPU STRATIX-II  
150 MHz 26220 (14.924)  
Core performance in terms of Dhrystones  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.