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DP80390CPU 参数 Datasheet PDF下载

DP80390CPU图片预览
型号: DP80390CPU
PDF下载: 下载PDF文件 查看货源
内容描述: 流水线的高性能8位微控制器 [Pipelined High Performance 8-bit Microcontroller]
分类和应用: 微控制器
文件页数/大小: 10 页 / 210 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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microcontroller is planned to use in portable  
and power critical applications.  
tions per second (many instructions executed  
in one clock cycle). The Off-chip Program  
Memory located in address space between  
1kB and 60kB, and above 64 kB is typically  
used for main code and constants. This part of  
the code is usually implemented as ROM,  
SRAM or FLASH device. Because of relatively  
long access time the program code executed  
from mentioned above devices must be  
fetched with additional Wait-States. Number of  
required Wait-States depends on memory ac-  
cess time and DP80390CPU clock frequency.  
In most cases the proper number of Wait-  
States cycles is between 2-5. The READY pin  
can be also dynamically modulated e.g. by  
SDRAM controller.  
DoCD™ Debug Unit – it’s a real-time hard-  
ware debugger provides debugging capability  
of a whole SoC system. In contrast to other on-  
chip debuggers DoCD™ provides non-intrusive  
debugging of running application. It can halt,  
run, step into or skip an instruction, read/write  
any contents of microcontroller including all  
registers, internal, external, program memo-  
ries, all SFRs including user defined peripher-  
als. Hardware breakpoints can be set and con-  
trolled on program memory, internal and exter-  
nal data memories, as well as on SFRs. Hard-  
ware breakpoint is executed if any write/read  
occurred at particular address with certain data  
pattern or without pattern. Two additional pins  
CODERUN, DEBUGACS indicate the sate of  
the debugger and CPU. CODERUN is active  
when CPU is executing an instruction. DE-  
BUGACS pin is active when any access is per-  
formed by DoCD™ debugger. The DoCD™  
system includes JTAG interface and complete  
set of tools to communicate and work with core  
in real time debugging. It is built as scalable  
unit and some features can be turned off to  
save silicon and reduce power consumption. A  
special care on power consumption has been  
taken, and when debugger is not used it is  
automatically switched in power save mode.  
Finally whole debugger is turned off when de-  
bug option is no longer used.  
0x7FFFFF  
Off chip Memory  
(implemented as ROM,  
SRAM or FLASH)  
0x00FFFF  
On chip Memory  
(implemented as RAM)  
0x00F000  
Off chip Memory  
(implemented as ROM,  
SRAM or FLASH)  
0x000400  
On-chip Memory  
(implemented as ROM)  
0x000000  
The figure below shows a typical Program  
Memories connections in system with  
DP80390CPU Microcontroller core.  
P R O G R A M C O D E S P A C E  
I M P L E M E N T A T I O N  
8
prgramdatai  
8
On-chip Memory  
(implemented as RAM)  
0 Wait-State access  
prgdatao  
prgramwr  
The figure below shows an example Pro-  
gram Memory space implementation in sys-  
tems with DP80390CPU Microcontroller core.  
The On-chip Program Memory located in ad-  
dress space between 0kB and 1kB is typically  
used for BOOT code with system initialization  
functions. This part of the code is typically im-  
plemented as ROM. The On-chip Program  
Memory located in address space between  
60kB and 64kB is typically used for timing criti-  
cal part of the code e.g. interrupt subroutines,  
arithmetic functions etc. This part of the code is  
typically implemented as RAM and can be  
loaded by the BOOT code during initialization  
phase from Off-chip memory or through RS232  
interface from external device. From the two  
mentioned above spaces program code is  
executed without wait-states and can achieve  
a top performance up to 200 million instruc-  
12  
10  
prgaddr  
On-chip Memory  
(implemented as ROM)  
0 Wait-State access  
8
prgromdata  
ASIC or FPGA  
chip  
DP80390CPU  
xdatai  
xdatao  
xaddr  
8
Off-chip Memory  
(implemented as  
FLASH, or SRAM)  
eg. 2-5 Wait-State  
access  
24  
xprgrd  
xprgwr  
Wait-States  
manager  
ready  
The described above implementation should be  
treated as an example. All Program Memory  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.