I M P L E M E N T A T I O N
Figures below show the typical DI2CMS im-
plementations in system with Standard/Fast
and High-speed devices.
P E R F O R M A N C E
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route (all key features
have been included):
VDD
RP
RP
Speed
grade
-3
Device
Logic Cells
Fmax
SDA
SCL
STRATIX-II
CYCOLNE-II
MERCURY
STRATIX
CYCLONE
APEX II
337
354
414
370
370
394
394
394
394
411
411
291
198
198
380 MHz
263 MHz
210 MHz
254 MHz
220 MHz
192 MHz
150 MHz
120 MHz
90 MHz
107 MHz
107 MHz
187 MHz
67 MHz
-6
-5
-5
-6
RS
RS
RS
RS
-7
APEX20KC
APEX20KE
APEX20K
ACEX1K
FLEX10KE
MAX 2
-7
-1
-1
-1
-1
-3
-5
-7
sdai
sda
sdao
open drain
Master
/Slave
device
DI2CMS
MAX 7000AE
MAX 3000A
scli
sclo
scl
49 MHz
Core performance in ALTERA® devices
open drain
sclhs
DI2CMS implementation in I2C-bus system with
Standard/Fast devices only
VDD
RP
RP
SDA
SCL
RS
RS
RS
RS
sdai
sda
sdao
open drain
Master
/Slave
device
DI2CMS
scli
sclo
scl
open drain
current-source
pull-up
sclhs
VDD
DI2CMS implementation in I2C-bus system with
High-speed devices
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are trademarks of their respective owners.
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http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
