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DI2CMS 参数 Datasheet PDF下载

DI2CMS图片预览
型号: DI2CMS
PDF下载: 下载PDF文件 查看货源
内容描述: I2C总线接口 - 主/从 [I2C Bus Interface - Master/Slave]
分类和应用:
文件页数/大小: 6 页 / 161 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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S Y M B O L  
B L O C K D I A G R A M  
Figure below shows the DI2CMS IP Core  
block diagram.  
datai(7:0)  
datao(7:0)  
rd  
we  
address(2:0)  
datai(7:0)  
Slave  
Address  
Input  
Filter  
sdai  
address(2:0)  
Shift  
Register  
datao(7:0)  
Output  
Register  
CPU  
Interface  
sdao  
sclhs  
sclo  
Send  
Data  
cs  
we  
rd  
scli  
sdai  
sdao  
Receive  
Data  
irq  
cs  
rst  
clk  
irq  
Control  
Register  
Arbitration  
Logic  
Control  
Logic  
Status  
Register  
Input  
Filter  
scli  
Clock Control  
Logic  
P I N S D E S C R I P T I O N  
Timer  
Output  
Register  
sclo  
PIN  
TYPE  
DESCRIPTION  
rst  
clk  
Output  
Register  
sclhs  
clk  
rst  
input  
input  
input  
input  
input  
input  
input  
input  
input  
Global clock  
Global reset  
CPU Interface – Performs the interface func-  
tions between DI2CMS internal blocks and  
microprocessor. Allows easy connection of the  
core to a microprocessor/microcontroller sys-  
tem.  
address(1:0)  
cs  
Processor address lines  
Chip select  
we  
Processor write strobe  
Processor read strobe  
I2C bus clock line (input)  
I2C bus data line (input)  
Processor data bus (input)  
rd  
scli  
Control Logic – Manages execution of all  
commands sent via interface. Synchronizes  
internal data flow.  
sdai  
datai(7:0)  
datao(7:0)  
sclo  
output Processor data bus (output)  
output I2C bus clock line (output)  
output High-speed clock line (output)  
output I2C bus data line (output)  
output Processor interrupt line  
Shift Register – Controls SDA line, performs  
data and address shifts during the data  
transmission and reception.  
sclhs  
sdao  
irq  
Control Register – Contains five control bits  
used for performing all types of I2C Bus  
transmissions.  
Status Register – Contains seven status bits  
that indicates state of the I2C Bus and the  
DI2CMS core.  
Input Filter – Performs spike filtering.  
Clock Control Logic – Performs clock syn-  
chronization, clock generation in master  
mode, and clock stretching in slave mode.  
Arbitration Logic – Performs arbitration dur-  
ing operations in multi-master systems.  
Timer – Allows operation from a wide range of  
the input frequencies. It is programmed by an  
user before transmission and can be repro-  
grammed to change the SCL frequency.  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.