● No internal tri-states
● Scan test ready
tion except One Year license where time of
use is limited to 12 months.
● Single Design license for
A P P L I C A T I O N S
○
VHDL, Verilog source code called HDL
Source
● Embedded microprocessor boards
● Consumer and professional audio/video
● Home and automotive radio
○
Encrypted, or plain text EDIF called Netlist
● One Year license for
Encrypted Netlist only
● Unlimited Designs license for
○
● Low-power applications
● Communication systems
○
○
HDL Source
Netlist
● Cost-effective reliable automotive systems
D E L I V E R A B L E S
● Upgrade from
♦
♦
Source code:
○
○
HDL Source to Netlist
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environ-
ment
Single Design to Unlimited Designs
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
♦
◊ HDL core specification
◊ Datasheet
♦
♦
♦
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
●
●
Delivery the IP Core updates, mi-
nor and major versions changes
Delivery the documentation up-
dates
Phone & email support
L I C E N S I N G
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
