The table below shows performance im-
provements of the NIOS-II processor with
DFPAU, compared to the same system with-
out the DFPAU coprocessor.
I M P R O V E M E N T S
DFPAU floating point instructions perform-
ance has been compared to standard C li-
brary functions delivered with every commer-
cial C compiler. Each program was executed
in the same system environments. Number of
clock periods were measured between input
data loading into work registers and output
result storing after operation. The results are
placed in table below. Improvement has been
computed as number of:
Device
Improvement
NIOS-II/s
1.0
7.5
5.9
6.8
NIOS-II+DFPAU (arithmetic)
NIOS-II+DFPAU (trigonometric)
NIOS-II+DFPAU (overall)
General performance improvements
(CPU clk) divided by (CPU+DFPAU clk), re-
quired to execute the same operation.
More details are available in core docu-
mentation.
12
8
The following table gives a survey about
the DP8051+DFPAU performance compared
to std 8051 microcontroller.
7,5
6,8
5,9
4
Device
80C51
DP8051
Improvement
1
1.0
7.3
91.0
0
DP8051+DFPAU
32-bit NIOS-II/s
General performance improvements
NIOS-II+DFPAU (arithmetic)
NIOS-II+DFPAU (trigonometric)
NIOS-II+DFPAU (overall)
150
100
50
91
IEEE-754 FP Instruction
Addition
Subtraction
Multiplication
Division
Square Root
Sine
Cosine
Improvement
6.4
6.5
5.1
6.5
12.9
5.2
5.4
5.8
7.2
7,3
1
0
Tangent
Arcs Tangent
Average speed improvement:
80C51
DP8051
DP8051+DFPAU
6.8
Improvements of particular operations
IEEE-754 FP Instruction
Addition
Subtraction
Multiplication
Division
Improvement
More details are available in core docu-
mentation.
73
60
65
182
392
10
Square Root
Sine
Cosine
10
Tangent
12
Arcs Tangent
17
Average speed improvement:
91
Improvements of particular operations
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