○
○
FXAM
– examine input data
– comparison
L I C E N S I N G
FUCOM
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
● Exceptions built-in routines
● Masks each exception indicator:
○ Precision lack PE
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implemen-
tation. It also permits FPGA prototyping be-
fore ASIC production.
○ Underflow result UE
○ Overflow result OE
Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
○ Invalid operand IE
○ Division by zero ZE
○ Denormal operand DE
● Fully configurable
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
● Fully synthesizable, static synchronous
design with no internal tri-states
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
D E L I V E R A B L E S
○ Encrypted, or plain text EDIF called Netlist
♦
♦
Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted Netlist or/and
◊ plain text EDIF netlist
VHDL & VERILOG test bench environ-
ment
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
◊ Active-HDL automatic simulation mac-
ros
◊ NCSim automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
♦
◊ HDL core specification
◊ Datasheet
♦
♦
♦
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
Delivery the IP Core updates, minor
and major versions changes
●
●
Delivery the documentation updates
Phone & email support
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
