欢迎访问ic37.com |
会员登录 免费注册
发布采购

DFPAU 参数 Datasheet PDF下载

DFPAU图片预览
型号: DFPAU
PDF下载: 下载PDF文件 查看货源
内容描述: 浮点运算协处理器 [Floating Point Arithmetic Coprocessor]
分类和应用:
文件页数/大小: 5 页 / 143 K
品牌: DCD [ DIGITAL CORE DESIGN ]
 浏览型号DFPAU的Datasheet PDF文件第1页浏览型号DFPAU的Datasheet PDF文件第2页浏览型号DFPAU的Datasheet PDF文件第4页浏览型号DFPAU的Datasheet PDF文件第5页  
Control Unit – manages execution of all  
instructions and internal operation required to  
execute particular function.  
S Y M B O L  
datai(31:0)1  
datao(31:0)1  
addr(4:2)2  
datai(31:0)1  
datao(31:0)1  
Mantissa  
we  
irq  
irq  
Interface  
addr(4:2)2  
we  
Align  
cs  
cs  
rst  
clk  
Exponent  
Shifter  
P I N S D E S C R I P T I O N  
Control  
Unit  
clk  
rst  
PIN  
TYPE  
DESCRIPTION  
clk  
rst  
cs  
Input Global system clock  
Input Global system reset  
Input Chip select for read/write  
Input Data bus input  
Interface – makes interface between exter-  
nal device and DFPAU internal 32-bit mod-  
ules. It contains data, control and status reg-  
isters. It can be configured to work with 8-,  
16- and 32-bit processors.  
datai[31:0]1  
addr[4:2]2  
we  
Input Register address to read/write  
Input Data write enable  
datao[31:0]1  
Output Data bus output  
int  
Output Interrupt request indicator  
P E R F O R M A N C E  
The following table gives a survey about  
the Core area and performance in the AL-  
TERA® devices after Place & Route (all key  
features have been included):  
1 – data bus can be configured as 8-, 16- or 32- bit  
depends on processor’s bus size  
2 – address bus is aligned to work with 8- (3:0), 16-  
(3:1) or 32- (4:2) bit processors  
Speed  
grade  
-1  
Device  
Logic Cells  
Fmax  
B L O C K D I A G R A M  
APEX20KE  
APEX20KC  
APEX-II  
CYCLONE  
CYCLONE-II  
STRATIX  
2640  
2640  
2640  
2410  
2280  
2210  
1680  
48 MHz  
57 MHz  
70 MHz  
91 MHz  
96 MHz  
115 MHz  
169 MHz  
-7  
-7  
-6  
-6  
-5  
-3  
Mantissa – performs operations on mantissa  
part of number. The addition, subtraction,  
multiplication, division, square root, compari-  
son and conversion operations are executed  
in this module. It contains mantissas and  
work registers.  
STRATIX-II  
Core performance in ALTERA® devices  
Exponent – performs operations on expo-  
nent part of number. The addition, subtrac-  
tion, shifting, comparison and conversion  
operations are executed in this module. It  
contains exponents and work registers.  
Align – performs the numbers analyze  
against IEEE-754 standard compliance. In-  
formation about the data classes are passed  
as result to appropriate internal module.  
Shifter – performs mantissa shifting during  
normalization, denormalization operations.  
Information about shifted-out bits are stored  
for rounding process.  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.