Information about shifted-out bits are stored
for rounding process.
P E R F O R M A N C E
The following table gives a survey about
the Core area and performance in the AL-
TERA® devices after Place & Route (all key
features have been included):
Control Coprocessor – manages execution
of all instructions and internal operation re-
quired to execute particular function.
Interface – makes interface between exter-
nal device and DFPAU-DP internal 32-bit
modules. It contains data, control and status
registers. It can be configured to work with 8-,
16- and 32-bit processors.
Speed
grade
-6
Device
Logic Cells
Fmax
CYCLONE
CYCLONE-II
STRATIX
3660
3630
3660
2800
79 MHz
71 MHz
84 MHz
110 MHz
-6
-5
-3
STRATIX-II
Core performance in ALTERA® devices
DFPAU-DP floating point instructions per-
formance has been compared to standard C
library functions delivered with every com-
mercial C compiler. Each program was exe-
cuted in the same system environments.
Number of clock periods were measured be-
tween input data loading into work registers
and output result storing after operation.
The results are placed in table below. Im-
provement has been computed as number of:
(NIOS-II CLK) divided by (NIOS-II+DFPAU-
DP CLK), required to execute particular in-
struction.
IEEE-754 FP Instruction
Addition
Improvement
12.0
Subtraction
Multiplication
Division
11.7
10.6
15.0
Square Root
Sine
21.5
11.8
Cosine
10.3
Tangent
10.1
Arcs Tangent
14.7
Average speed improvement:
13.1
More details are available in core docu-
mentation.
The following table gives a survey about
the 32-bit NIOS-II+DFPAU-DP performance
compared to 32-bit NIOS-II.
Device
Improvement
NIOS-II
1.0
14.1
11.7
13.1
NIOS-II+DFPAU (arithmetic)
NIOS-II+DFPAU (trigonometric)
NIOS-II+DFPAU (overall)
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