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DFPAU-DP 参数 Datasheet PDF下载

DFPAU-DP图片预览
型号: DFPAU-DP
PDF下载: 下载PDF文件 查看货源
内容描述: 浮点运算协处理器的双精度 [Floating Point Arithmetic Coprocessor Double Precision]
分类和应用:
文件页数/大小: 6 页 / 136 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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K E Y F E A T U R E S  
D E L I V E R A B L E S  
Direct replacement for C double, float  
software functions such as: +, -, *, /,==,  
!=,>=, <=, <, >  
Source code:  
VHDL Source Code or/and  
VERILOG Source Code or/and  
Encrypted Netlist or/and  
plain text EDIF netlist  
VHDL & VERILOG test bench environ-  
ment  
Configurability of all available functions  
C interface supplied for all popular compil-  
ers: GNU C/C++, 8051 compilers  
No programming required  
Active-HDL automatic simulation mac-  
ros  
IEEE-754 Double precision real format  
support – double type  
NCSim automatic simulation macros  
ModelSim automatic simulation macros  
Tests with reference responses  
Technical documentation  
Installation notes  
HDL core specification  
Datasheet  
Synthesis scripts  
Example application  
Technical support  
IP Core implementation support  
3 months maintenance  
IEEE-754 Single precision real format  
support – float type  
8-bit, 16-bit 32-bit and 52-bit integers for-  
mat supported – integer types  
Flexible arguments and result registers  
location  
Performs the following functions:  
FADD, FSUB – addition, subtraction  
FMUL, FDIV  
FSQRT  
– multiplication, division  
– square root  
Delivery the IP Core updates, minor  
and major versions changes  
Delivery the documentation updates  
Phone & email support  
FXAM  
– examine input data  
– comparison  
FUCOM  
FCLD, FILD  
– 8-bit, 16-bit integer to dou-  
ble  
FLLD, FELD  
– 32-bit, 52-bit integer to  
– double to 8-bit, 16-bi inte-  
– double to 32-bit, 52-bit in-  
double  
FCST, FIST  
ger  
FLST, FEST  
teger  
FFLD  
FFST  
– float to double  
– double to float  
Exceptions built-in routines  
Masks each exception indicator:  
Precision lack PE  
Underflow result UE  
Overflow result OE  
Invalid operand IE  
Division by zero ZE  
Denormal operand DE  
Fully configurable  
Fully synthesizable, static synchronous  
design with no internal tri-states  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.