L I C E N S I N G
P I N S D E S C R I P T I O N
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
PIN
TYPE
DESCRIPTION
clk
rst
cs
Input Global system clock
Input Global system reset
Input Chip select for read/write
Input Data bus input
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implemen-
tation. It also permits FPGA prototyping be-
fore ASIC production.
datai[31:0]1
addr[4:2]2
we
Input Register address to read/write
Input Data write enable
Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
datao[31:0]1
Output Data bus output
irq
Output Interrupt request indicator
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
1 – data bus can be configured as 8-, 16- or 32- bit
depends on processor’s bus size
2 – address bus is aligned to work with 8- (3:0), 16-
(3:1) or 32- (4:2) bit processors
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
B L O C K D I A G R A M
Mantissa – performs operations on mantissa
part of number. The addition, subtraction,
multiplication, division, square root, compari-
son and conversion operations are executed
in this module. It contains mantissas and
work registers.
○ Encrypted, or plain text EDIF called Netlist
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
datai(31:0)1
datao(31:0)1
Mantissa
S Y M B O L
irq
Interface
addr(4:2)2
we
datai(31:0)1
addr(4:2)2
we
datao(31:0)1
irq
Align
cs
Exponent
Shifter
cs
rst
clk
clk
rst
Control
Unit
Exponent – performs operations on expo-
nent part of number. The addition, subtrac-
tion, shifting, comparison and conversion
operations are executed in this module. It
contains exponents and work registers.
Align – performs the numbers analyze
against IEEE-754 standard compliance. In-
formation about the data classes are passed
as result to appropriate internal module.
Shifter – performs mantissa shifting during
normalization, denormalization operations.
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DCD [ DIGITAL CORE DESIGN ]
