P E R F O R M A N C E
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Speed
grade
-6
Device
Logic Cells
Fmax
CYCLONE
CYCLONE 2
STRATIX
STRATIX 2
STRATIXGX
MERCURY
EXCALIBUR
APEX II
APEX20KC
APEX20KE
APEX20K
ACEX1K
301
303
301
248
301
350
340
340
340
340
340
363
363
190 MHz
222 MHz
213 MHz
283 MHz
212 MHz
222 MHz
137 MHz
145 MHz
143 MHz
122 MHz
83 MHz
-6
-5
-3
-5
-5
-1
-7
-7
-1
-1
-1
-1
99 MHz
98 MHz
FLEX10KE
Core performance in ALTERA® devices
D 1 6 X 5 0 U A R T S F A M I L Y O V E R V I E W
The family of DCD D16X50 UART IP Cores combine a high–performance, low cost, and small
compact size, offering the best price/performance ratio in the IP Market. The DCD’s Cores are
dedicated for use in cost-sensitive consumer products, computer peripherals, office automation,
automotive control systems, security and telecommunication applications.
The D16X50 IP Cores are written in pure VHDL/VERILOG HDL languages which make them
technologically independent. All of the D16X50 IP Cores can be fully customized according to
customer needs.
Design
D16450
D16550
D16750
D16552
D16752
D16754
1
1
1
2
2
4
-
-
-
-
-
-
-
-
-*
-*
-*
-*
-*
-*
2* 16
2* 64
4* 16
4* 64
8* 64
-
-*
-*
-*
-*
*-Optional
D16X50 family of Configurable UARTs with FIFO IP Cores
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are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
