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rst
clk
rclk
C O N F I G U R A T I O N
baudout
The following parameters of the D16450 core
can be easy adjusted to requirements of
intr
baudclk
datai(7:0)
address(2:0)
datao(7:0)
dedicated
application
and
technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
wr
rd
cs
ddis
D16450
so
si
-
-
enable
disable
cts
dsr
dcd
ri
rts
dtr
out1
out2
Baud generator
•
•
•
•
•
-
-
enable
disable
External RCLK source
External BAUDCLK source
Modem Control logic
SCR Register
baudclken
rclken
-
-
enable
disable
-
-
enable
disable
P I N S D E S C R I P T I O N
-
-
enable
disable
PIN
TYPE
DESCRIPTION
rst
input Global reset
D E S I G N F E A T U R E S
clk
input Global clock
The functionality of the D16450 core was
datai[7:0]
addr[2:0]
cs
input Parallel data input
input Address bus
based on the Texas Instruments TL16C450.
The following characteristics differentiate the
D16450 from Texas Instruments devices:
● The bi-directional data bus has been split
into two separate buses: datai(7:0),
datao(7:0)
input Chip select input
input Write input
wr
rd
input Read input
rclk
input Receiver clock
baudclk
si
input Baud generator clock
input Serial data input
input Clear to send input
input Data set ready input
input Data carrier detect input
input Ring indicator input
input Baud generator clock enable
input Receiver clock enable
output Baud generator output
output Parallel data output
output Serial data output
output Driver disable output
output Request to send output
output Data terminal ready output
output Output 1
● Signals rd2 and wr2, xin, and xout have
been removed from interface
cts
● Signal ADS and address latch have been
dsr
removed
dcd
ri
● The DLL, DLM and THR registers are
baudclken
rclken
baudout
datao[7:0]
so
reset to all zeros
● TEMT and THRE bits of Line Status
Register, are reset during the second
clock rising edge following a THR write
● RCLK clock is replaced by global clock
ddis
CLK, internally divided by BAUD factor.
rts
● Asynchronous microcontroller interface is
dtr
replaced by equivalent Universal interface
out1
out2
intr
output Output 2
● All latches implemented in original 16450
devices are replaced by equivalent flip-flop
registers, with the same functionality
output Interrupt request output
Note: When enabled RCLK and BAUDCLK pins
frequency should be at least two times lower
than CLK, 2*fRCLK< fCLK
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
