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D16450 参数 Datasheet PDF下载

D16450图片预览
型号: D16450
PDF下载: 下载PDF文件 查看货源
内容描述: 可配置的UART [Configurable UART]
分类和应用:
文件页数/大小: 6 页 / 188 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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Fully  
programmable  
serial-interface  
D E L I V E R A B L E S  
Source code:  
characteristics:  
5-, 6-, 7-, or 8-bit characters  
VHDL Source Code or/and  
VERILOG Source Code or/and  
Encrypted, or plain text EDIF netlist  
VHDL & VERILOG test bench  
environment  
Active-HDL automatic simulation macros  
ModelSim automatic simulation macros  
Tests with reference responses  
Technical documentation  
Installation notes  
Even, odd, or no-parity bit generation and  
detection  
1-, 1½-, or 2-stop bit generation  
Baud generation  
Complete status reporting capabilities  
Line break generation and detection.  
Internal diagnostic capabilities:  
HDL core specification  
Datasheet  
Synthesis scripts  
Example application  
Technical support  
Loop-back controls for communications link  
fault isolation  
Break, parity, overrun, framing error  
simulation  
Technology independent HDL Source  
IP Core implementation support  
3 months maintenance  
Code  
Delivery the IP Core updates, minor  
and major versions changes  
Delivery the documentation updates  
Phone & email support  
Full prioritized interrupt system controls  
Fully synthesizable static design with no  
internal tri-state buffers  
A P P L I C A T I O N S  
Serial Data communications applications  
L I C E N S I N G  
Comprehensible and clearly defined licensing  
methods without royalty fees make using of IP  
Core easy and simply.  
Modem interface  
Single Design license allows use IP Core in  
single  
FPGA  
bitstream  
and  
ASIC  
implementation.  
Unlimited Designs, One Year licenses allow  
use IP Core in unlimited number of FPGA  
bitstreams and ASIC implementations.  
In all cases number of IP Core instantiations  
within a design, and number of manufactured  
chips are unlimited. There is no time  
restriction except One Year license where  
time of use is limited to 12 months.  
Single Design license for  
VHDL, Verilog source code called HDL  
Source  
Encrypted, or plain text EDIF called Netlist  
One Year license for  
Encrypted Netlist only  
Unlimited Designs license for  
HDL Source  
Netlist  
Upgrade from  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.  
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