DM9016
3-port switch with Processor Interface
10.4.2 Processor I/O Read Timing
T1
T2
CS#,CMD
IOR#
T4
T3
SD0~31
T6
T5
Symbol
T1
Parameter
CS#,CMD valid to IOR# valid
Min.
5
Typ.
Max.
Unit
ns
T2
T3
T4
IOR# invalid to CS#,CMD invalid
IOR# width
IOR# invalid to next IOR#/IOW# valid
When read DM9016 register
5
20
2
ns
ns
clk*
T4
IOR# invalid to next IOR#/IOW# valid
When read DM9016 memory with F0h register
4
1
clk*
clk*
T3+T4 IOR# invalid to next IOR#/IOW# valid
When read DM9016 memory with F2h register
T5
T6
System Data(SD) Delay time
IOR# invalid to System Data(SD) invalid
25
10
ns
ns
Note: the Unit: clk is under the internal system clock 50MHz..
80
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009