DM9016
3-port switch with Processor Interface
6.71 VLAN Priority Map Registers (D0H~D1H)
Define the 3-bit of priority field VALN mapping to 2-bit priority queue number
D0H:
Bit
7:6
5:4
3:2
1:0
Name
TAG3
TAG2
TAG1
TAG0
Default
Description
PHE1,RW VLAN priority tag value = 03H
PHE1,RW VLAN priority tag value = 02H
PHE0,RW VLAN priority tag value = 01H
PHE0,RW VLAN priority tag value = 00H
D1H:
Bit
7:6
5:4
3:2
1:0
Name
TAG7
TAG6
TAG5
TAG4
Default
Description
PHE3,RW VLAN priority tag value = 07H
PHE3,RW VLAN priority tag value = 06H
PHE2,RW VLAN priority tag value = 05H
PHE2,RW VLAN priority tag value = 04H
6.72 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0
MRCMDX
X,RO
Read data from RX SRAM.
After the read of this command, the read pointer of internal SRAM is unchanged.
And the DM9016 starts to pre-fetch the SRAM data to internal data buffers.
6.73 Memory Data Read Command with Address Increment Register (F2H)
When register FFH bit 7 is “0”, register F5H value will be returned to 0000H, if 16K-byte boundary is reached.
When register FFH bit 7 is “1”, register F5H value will be returned to 0000H, if processor port receive memory byte boundary
address RX memory size, defined in register 3FH with default 1F00H, is reached.
Bit
Name
Default
Description
7:0
MRCMD
X,RO
Read data from RX SRAM.
After the read of this command, the read pointer is increased by 1,2, or 4,
depends on the operator mode (8-bit,16-bit and 32-bit respectively)
6.74 Memory Data Read address Register (F4H)
When register FFH bit 7 is “0”, register F5H and F4H can be used as memory byte address to read internal 64K-byte memory.
When register FFH bit 7 is “1”, register F5H and F4H can be used as processor port receive memory byte address with
memory space range from 0 to (RX memory size - 1), defined in register 3FH with default 1EFFH.
Bit
Name
Default
Description
7:0
MDRAL
PHS0,RW Memory Data Read_ address Low Byte
6.75 Memory Data Read address Register (F5H)
Bit
7-6
5:4
3:0
Name
RESERVED
Default
P0,RO
Description
Reserved
MDRAH65 PHS0,RW Port number
MDRAH40 PHS0,RW Memory Data Read_ address [11:8]
Preliminarydatasheet
DM9016-13-DS-P01
March 26, 2009
43
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
