DM9016
3-port switch with Processor Interface
6.76 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Description
7:0
MWCMDX
X,WO
Write data to TX SRAM.
After the write of this command, the write pointer is unchanged
6.77 Memory Data Write Command with Address Increment Register (F8H)
Bit
Name
Default
Description
7:0
MWCMD
X,WO
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1, 2, or 4,
depends on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.78 Memory Data Write address Register (FAH)
Bit
Name
Default
Description
7:0
MDRAL
PHS0,RW Memory Data Write_ address Low Byte
6.79 Memory Data Write address Register (FBH)
Bit
7,6
5:4
3:0
Name
RESERVED
Default
P0,RO
Description
Description
Description
Reserved
MDRAH65 PHS0,RW Port number
MDRAH40 PHS0,RW Memory Data Write_ address [11:8]
6.80 TX Packet Length Register (FCH~FDH)
Bit
7:0
7:0
Name
TXPLH
TXPLL
Default
PHS0,RW TX Packet Length High byte
PHS0,RW TX Packet Length Low byte
6.81 Interrupt Status Register (FEH)
Bit
Name
Default
7:6
M_WIDTH
T0, RO
Memory Bus Width
Bit 7 Bit 6
0
0
1
1
0
1
0
1
16-bit mode
32-bit mode
8-bit mode
Reserved
5
4
3
2
1
0
LNKCHG
CNT_ERR
ROO
PHS0,RW/C1 Link Status Change of port 0 or 1
PHS0,RW/C1 BLK Table Counter error
PHS0,RW/C1 Receive Overflow Counter Overflow
PHS0,RW/C1 Receive Overflow
PHS0,RW/C1 Packet Transmitted
PHS0,RW/C1 Packet Received
ROS
PT
PR
6.82 Interrupt Mask Register (FFH)
Bit
7
6
5
4
3
2
1
0
Name
TXRX_EN
RESERVED
LNKCHGI
CNT_ERR
ROOI
Default
PHS0,RW
0,RO
Description
Enable the SRAM read/write pointer used as transmit /receive address.
Reserved
PHS0,RW
Enable Link Status Change of port 0 or 1Interrupt
PHS0,RW/C1 Enable BLK Table Counter error interrupt
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
Enable Packet Received Interrupt
ROI
PTI
PRI
44
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
