DM9016
3-port switch with Processor Interface
6.66 MIB counter Port Index Register (80H)
Bit
7
6
Name
READY
MIB_DIS
Default
P0,RO
Description
MIB counter data is ready
PHS0,RW MIB Counter Disabled
This bit has the opposite meaning in write and read:
When write:
1: MIB counter disabled
When read:
1: MIB counter is enabled
Reserved
PHS0,RW MIB counter index 0~9, each counter is 32-bit in Register 81h~84h.
Write the MIB counter index to this register before read them.
5
4:0
RESERVED
INDEX
0,RO
6.67 MIB counter Data Register (81H~84H)
Bit
Name
Default
X,RO
X,RO
X,RO
X,RO
Description
81H
82H
83H
84H
Counter0
Counter1
Counter2
Counter3
Counter’s data bit 7~0
Counter’s data bit 15~8
Counter’s data bit 23~16
Counter’s data bit 31~24
MIB counter: RX Byte Counter Registers (00H)
MIB counter: RX Uni-cast Packet Counter Registers (01H)
MIB counter: RX Multi-cast Packet Counter Registers (02H)
MIB counter: RX Discard Packet Counter Registers (03H)
MIB counter: RX Error Packet Counter Registers (04H)
MIB counter: TX Byte Counter Registers (05H)
MIB counter: TX Uni-cast Packet Counter Registers (06H)
MIB counter: TX Multi-cast Packet Counter Registers (07H)
MIB counter: TX Discard Packet Counter Registers (08H)
MIB counter: TX Error Packet Counter Registers (09H)
6.68 Per Port RX Packet Length Control Register (88H)
Bit
7:2
1:0
Name
RESERVED
PKT_LEN
Default
PE0,RO
Description
Reserved
PE0,RW Accept Packet Length
0X: 1536-byte
10: 1800-byte
11: 2032-byte
Preliminarydatasheet
DM9016-13-DS-P01
March 26, 2009
39
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
