DM9016
3-port switch with Processor Interface
5.10 Strap Pins Table
1: pull-high 1K~10K, 0: default floating.
5.10.1 Strap pin in 3-port mode
Pin No.
Pin Name
Description
Processor Data Bus Width
50
51
EECK
EEDO
EECK
EEDO data width
0
0
1
1
0
1
0
1
16-bit (default)
32-bit
8-bit
(reserved)
Source of System Clock
52
55
EECS
MDC
0: system clock is internal 50MHz clock (default)
1: use SCLK pin as system clock
Polarity of IRQ
0: IRQ pin high active (default)
1: IRQ pin low active
58
59
TXD2_3
TXD2_2
ISA pin control
0: GP6/5 as normal usage (default)
1: GP6 as IO16, GP5 as IOWAIT
Port 2 force mode
0: Port 2 status from external PHY (N-way)
1: Port 2 in force mode
60
61
TXD2_1
TXD2_0
Port 2 mode
TXD2_1, TXD2_0
0
0
1
1
0
1
0
1
Port 2 is MII mode (default)
Port 2 is Reverse-MII mode
Port 2 is RMII mode
Reserved
63
TXEN2
GP2
Output Type of IRQ
0: IRQ pin is force output (default)
1: IRQ pin is open-collect
Port 2 Force mode Speed is: (when TXD2_2 pulled high)
115
114
113
0: 100Mbps
1: 10Mbps
GP3
Port 2 Force mode Duplex is : (when TXD2_2 pulled high)
0: full-duplex
1: half-duplex
GP4
Port 2 Force mode Link is: (when TXD2_2 pulled high)
0: link
1: non-link
18
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
