DM9016
3-port switch with Processor Interface
5. Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, PD=internal pull-low (about 50K Ohm)
# = asserted Low
5.1 Processor Bus Interface
Pin No.
Pin Name
I/O
Description
1
CMD
I
Command Type
When high, the access of this command cycle is DATA
port
When low, the access of this command cycle is INDEX
port
2
3
5
6
CS#
IOW#
I
I
Processor Chip select Command
Processor Write Command
Processor Read Command
Interrupt Request
IOR#
I
IRQ
O
7,8,9,10,12,13,14,15,
16,17,19,20,22,23,25,26
28,29,30,31,33,34,36,37,
38,39,41,42,43,44,46,47
110
SD0~15
SD16~31
WOL
I/O Processor Data Bus bit 0~15
I/O Processor Data Bus bit 16~31 or
General purpose pins when data bus is in 16-bit mode
O
Issue a wake up signal when wake up event occurred.
5.2 General and LED pins
Pin No.
Pin Name
I/O
Description
118,117,115,114,
113,112,111
119,121,122,123,
124,126,127,128
GP0~6
I/O General I/O Ports
Registers GPCR and GPR can program these pins
I/O Bandwidth LED
BWLED0~7
5.3 P2 MII / RMII / Reverse MII Interfaces
5.3.1 MII Interfaces
Pin No.
55
56
Pin Name
MDC
MDIO
I/O
O,PD
I/O
Description
MII Serial Management Data Clock
MII Serial Management Data
Port 2 MII Transmit Data
58,59,60,61
TXD2_3~0
O,PD
4-bit nibble data outputs (synchronous to the TXC2)
63
TXE2
O,PD
Port 2 MII Transmit Enable
64
TXC2
O,PD
Port 2 MII Transmit Clock
65
66
67
68
CRS2
COL2
RXER2
RXC2
RXDV2
RXD2_3~0
I
I
I
I
I
I
Port 2 MII Carrier Sense
Port 2 MII Collision Detect
Port 2 MII Receive Error
Port 2 MII Receive Clock
Port 2 MII Receive Data Valid
Port 2 MII Receive Data
70
71,72,73,74
4-bit nibble data input (synchronous to RXC2)
14
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
