DM9016
3-port switch with Processor Interface
3. Features
Ethernet Switch with two 10/100Mb PHY, one MII/RMII/Reverse-MII port, and a flexible 8,
16, or 32-bit general processor bus interface
Store and Forward switching approach
Support HP Auto-MDIX
Support up-to 1K Unicast MAC addresses
Support IEEE 802.3x Flow Control in Full-duplex mode
Support Back Pressure Flow Control in Half-duplex mode
Per port supports ingress or egress bandwidth rate control
Support Broadcast/Multicast Storm Suppression
Support maximum packet length up to 1536(default)/1800/2032 bytes
Support head of Line (HOL) blocking prevention
Support MIB counters for diagnostic
General processor bus is slave architecture
General processor bus driving capability is adjustable
General processor bus supports TCP/UDP/IPv4 checksum offload
EEPROM interface for power up configuration
Support EEPROM 93C46/93C56 with auto-detecting
Driving capability of TXD/TXE of MII is adjustable
Per port supports 4 level priority queues by Port-based, 802.1p VLAN, and IP TOS priority.
The priority queue can be set at WRR(Weighted Round Robin) or Strictly(High priority
queue first)
Support 802.1Q VLAN up-to 16 VLAN group.
Support VLAN ID tag/untag options
MAC Address Table is accessible
Support 256-entry multicast address table
Support port security function
Support 32 entry hardware-based IGMP Snooping V1, V2
Support IPv6 Multicast Listener Discovery (MLD) Snooping V1
Support Spanning Tree Protocol
128 QFP package with 0.18um technology
1.8V internal core, 3.3V I/O with 5V tolerant
12
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
