DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.29 TRANSMIT CHECK SUM CONTROL REGISTER (31H).................................................................................................... 24
6.30 RECEIVE CHECK SUM CONTROL STATUS REGISTER (32H).......................................................................................... 24
6.31 EXTERNAL PHYCEIVER ADDRESS REGISTER (33H).................................................................................................... 24
6.32 GENERAL PURPOSE CONTROL REGISTER 2 (34H) ....................................................................................................... 25
6.33 GENERAL PURPOSE REGISTER 2 (35H) ....................................................................................................................... 25
6.34 GENERAL PURPOSE CONTROL REGISTER 3 (36H) ....................................................................................................... 25
6.35 GENERAL PURPOSE REGISTER 3 (37H) ....................................................................................................................... 25
6.36 PROCESSOR BUS CONTROL REGISTER (38H) .............................................................................................................. 25
6.37 INT PIN CONTROL REGISTER (39H)............................................................................................................................ 26
6.38 MONITOR REGISTER 1 (40H) ...................................................................................................................................... 26
6.39 MONITOR REGISTER 2 (41H) ...................................................................................................................................... 26
6.40 SYSTEM CLOCK TURN ON CONTROL REGISTER (50H)............................................................................................... 26
6.41 RESUME SYSTEM CLOCK CONTROL REGISTER (51H) ................................................................................................. 26
6.42 MEMORY DATA PRE-FETCH READ COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F0H)............................... 26
6.43 MEMORY DATA READ COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F1H) ................................................. 27
6.44 MEMORY DATA READ COMMAND WITH ADDRESS INCREMENT REGISTER (F2H)........................................................ 27
6.45 MEMORY DATA READ ADDRESS REGISTER (F4H~F5H).............................................................................................. 27
6.46 MEMORY DATA WRITE COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F6H)................................................ 27
6.47 MEMORY DATA WRITE COMMAND WITH ADDRESS INCREMENT REGISTER (F8H)......................................................... 27
6.48 MEMORY DATA WRITE ADDRESS REGISTER (FAH~FBH)............................................................................................. 27
6.49 TX PACKET LENGTH REGISTER (FCH~FDH) ............................................................................................................. 27
6.50 INTERRUPT STATUS REGISTER (FEH).......................................................................................................................... 28
6.51 INTERRUPT MASK REGISTER (FFH)............................................................................................................................ 28
7. EEPROM FORMAT ........................................................................................................................................................ 29
8. MII REGISTER DESCRIPTION................................................................................................................................... 30
8.1 BASIC MODE CONTROL REGISTER (BMCR) - 00 .......................................................................................................... 31
8.2 BASIC MODE STATUS REGISTER (BMSR) - 01 .............................................................................................................. 32
8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) - 02 ........................................................................................................ 33
8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) - 03 ........................................................................................................ 33
8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) - 04.................................................................................... 33
8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05..................................................................... 34
8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) - 06............................................................................................. 35
8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) - 16.................................................................................. 35
8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) - 17 ........................................................... 37
8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) - 18............................................................................................... 38
8.11 POWER DOWN CONTROL REGISTER (PWDOR) - 19 ................................................................................................... 38
8.12 (SPECIFIED CONFIG) REGISTER – 20............................................................................................................................ 39
9. FUNCTIONAL DESCRIPTION..................................................................................................................................... 40
9.1 HOST INTERFACE .......................................................................................................................................................... 40
9.2 DIRECT MEMORY ACCESS CONTROL ............................................................................................................................ 40
9.3 PACKET TRANSMISSION ................................................................................................................................................ 40
9.4 PACKET RECEPTION ...................................................................................................................................................... 40
9.5 100BASE-TX OPERATION ............................................................................................................................................. 40
9.5.1 4B5B Encoder ...................................................................................................................................................... 41
9.5.2 Scrambler............................................................................................................................................................. 41
9.5.3 Parallel to Serial Converter................................................................................................................................. 41
9.5.4 NRZ to NRZI Encoder.......................................................................................................................................... 41
9.5.5 MLT-3 Converter.................................................................................................................................................. 41
9.5.6 MLT-3 Driver ....................................................................................................................................................... 41
9.5.7 4B5B Code Group................................................................................................................................................ 42
9.6 100BASE-TX RECEIVER ............................................................................................................................................... 43
Preliminary
3
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
