DM9000BI
Industrial-grade Ethernet Controller with General Processor Interface
General I/O Ports
28,29,31 GP3,GP2,GP1
I/O Registers GPCR and GPR can program these pins
These pins are input ports at default.
5.2 EEPROM Interface
Pin No.
19
Pin Name
EEDIO
Type
Description
IO Data to EEPROM
Clock to EEPROM
I/O,PD
This pin is also used as the strap pin of the polarity of the INT pin
When this pin is pulled high, the INT pin is low active; otherwise the INT
pin is high active
20
21
EECK
EECS
O,PD
O,PD
Chip Select to EEPROM
This pin is also used as a strap pin to define the internal memory data bus
width. When it is pulled high, the memory access bus is 8-bit; Otherwise it
is 16-bit.
5.3 Clock Interface
Pin No.
43
Pin Name
Type
Description
Crystal 25MHz Out
X2
X1
O
I
44
Crystal 25MHz In
5.4 LED Interface
Pin No.
Pin Name
Type
Description
Speed LED
I/O Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY.
This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit
mode.
39
LED1
LED2
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
38
I/O In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM
setting in 16-bit mode.
5.5 10/100 PHY/Fiber
Pin No.
Pin Name
Type
I
Description
Fiber-optic Signal Detect
46
SD
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Band gap Ground
48
1
BGGND
BGRES
P
I/O
P
Band gap Pin
1.8V power output for TP RX
1.8V power output for TP TX
2
RXVDD18
TXVDD18
9
P
Preliminary
11
Version: DM9000BI-13-DS-P02
January 17, 2008
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
