欢迎访问ic37.com |
会员登录 免费注册
发布采购

DM562P_04 参数 Datasheet PDF下载

DM562P_04图片预览
型号: DM562P_04
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的V.90数据/传真/语音/扬声器调制解调器设备的单芯片与内存内置 [V.90 Integrated Data/ Fax/Voice/Speakerphone Modem Device Single Chip with Memory Built in]
分类和应用: 调制解调器
文件页数/大小: 48 页 / 1161 K
品牌: DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
 浏览型号DM562P_04的Datasheet PDF文件第39页浏览型号DM562P_04的Datasheet PDF文件第40页浏览型号DM562P_04的Datasheet PDF文件第41页浏览型号DM562P_04的Datasheet PDF文件第42页浏览型号DM562P_04的Datasheet PDF文件第44页浏览型号DM562P_04的Datasheet PDF文件第45页浏览型号DM562P_04的Datasheet PDF文件第46页浏览型号DM562P_04的Datasheet PDF文件第47页  
DM562P  
V.90 Integrated Data/ Fax/Voice/Speakerphone  
Modem Device Single Chip with Memory Built in  
DM6580 Functional Description  
In this chip, we could roughly divide it into two major  
parts: digital portion and analog portion. The  
functional blocks are described separately in this  
section. The analog circuits include a sigma-delta  
modulator/demodulator, decimation/interpolation  
filters, a speaker driver, low-pass filter and certain  
logic circuits. The digital circuits is composed of  
Tx/Rx clock generator/PLL, serial port, serial/parallel  
conversions and control registers. All the clock  
information the analog circuits need should be  
provided by the digital clock system since the best  
sampling instant of A/D and D/A depends on the  
received signal and transmit signals. The data format  
of A/D and D/A is 2's complement.  
The master clock (FQ) is obtained from an external  
signal connected to CLKIN. The different transmit  
and receive clocks are obtained by master clock  
frequency division in several programmable counters.  
The Tx and Rx clocks can be synchronized on  
external signals by performing the phase shifts in the  
frequency division process. Two independent digital  
phase locked loops are implemented using this  
principle, one for transmit clock system, the other,  
receive clock. The tracking of the transmit clock is  
automatically done by the transmit DPLL circuit. The  
receive DPLL circuit is controlled by the host  
processor and it is actually an adjustable phase  
shifter.  
DM6580 Register Description  
Register  
TxCR0  
TxCR1  
TxCR2  
D11  
D10  
D9  
D8  
X1  
D
D7  
X0  
M1  
F0  
D6  
N3  
M0  
W
D5  
N2  
D4  
N1  
F
D3  
N0  
Y
D2  
R0  
D1  
S
D0  
T
Programme  
dFunctions  
R1  
X3  
X2  
Tx Data Rate  
Clock  
Q1  
Q0  
U2  
U1  
U0  
VF  
Tx Baud  
sample Clock  
Miscellaneou  
s control  
Reserved  
Vol1  
Q1  
Vol2  
F1  
ATT  
LTX  
LC  
SST  
EMX  
TxTest  
RxCR0  
R1  
H2  
H1  
D
H0  
M1  
N3  
M0  
N2  
Q0  
N1  
P
N0  
Y
R0  
U2  
S
T
Rx Data Rate  
Clock  
Rx Baud  
SampleClock  
Rx Phase  
RxCR1  
RxCR2  
RxTest  
RST  
-6dB  
U1  
U0  
LL  
PS4  
PS3  
PS2  
PS1  
PS0  
AP2  
AP1  
AP0  
Shift Control  
Reserved  
Final  
43  
Version: DM562P-DS-F01  
February 02, 2004  
 复制成功!