DS2506
Overdrive Skip ROM [3CH]
On a single-drop bus this command can save time by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive
Skip ROM sets the DS2506 in the Overdrive Mode (OD=1). All communication following this command
has to occur at Overdrive Speed until a reset pulse of minimum 480 µs duration resets all devices on the
bus to regular speed (OD=0).
When issued on a multidrop bus this command will set all Overdrive-capable devices into Overdrive
mode. To subsequently address a specific Overdrive-capable device, a reset pulse at Overdrive speed has
to be issued followed by a Match ROM or Search ROM command sequence. This will shorten the time
for the search process. If more than one slave supporting Overdrive is present on the bus and the
Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wire-AND result).
Overdrive Match ROM [69H}
The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive
Speed, allows the bus master to address a specific DS2506 on a multidrop bus and to simultaneously set it
in Overdrive Mode. Only the DS2506 that exactly matches the 64-bit ROM sequence will respond to the
subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive
Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit
ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a reset
pulse of minimum 480 µs duration. The Overdrive Match ROM command can be used with a single or
multiple devices on the bus.
1-Wire Signalling
The DS2506 requires strict protocols to insure data integrity. The protocol consists of five types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data
and Program Pulse. All these signals except presence pulse are initiated by the bus master. The DS2506
can communicate at two different speeds, regular speed and Overdrive Speed. If not explicitly set into the
Overdrive Mode, the DS2506 will communicate at regular speed. While in Overdrive Mode the fast
timing applies to all communication-related wave forms.
The initialization sequence required to begin any communication with the DS2506 is shown in Figure 9.
A Reset Pulse followed by a Presence Pulse indicates the DS2506 is ready to accept a ROM command.
The bus master transmits (TX) a reset pulse (tRSTL, minimum 480 µs at regular speed, 48 µs at Overdrive
Speed). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled
to a high state via the pullup resistor. After detecting the rising edge on the data pin, the DS2506 waits
(tPDH, 15-60 µs at regular speed, 2-6 µs at overdrive speed) and then transmits the presence pulse (tPDL
,
60-240 µs at regular speed, 8-24 µs at Overdrive Speed).
A Reset Pulse of 480 µs or longer will exit the Overdrive Mode returning the device to regular speed. If
the DS2506 is in Overdrive Mode and the Reset Pulse is no longer than 80 µs the device will remain in
Overdrive Mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 10. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2506 to the master
by triggering a delay circuit in the DS2506. During write time slots, the delay circuit determines when the
DS2506 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
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DALLAS [ DALLAS SEMICONDUCTOR ]
