DS2154
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
(LSB)
T1E1
0
0
0
ID3
ID2
ID1
ID0
SYMBOL
POSITION NAME AND DESCRIPTION
T1E1
ID3
IDR.7
IDR.3
T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
Chip Revision Bit 3. MSB of a decimal code that represents the
chip revision.
ID2
ID1
ID0
IDR.1
IDR.2
IDR.0
Chip Revision Bit 2.
Chip Revision Bit 1.
Chip Revision Bit 0. LSB of a decimal code that represents the
chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
-
-
FRC
SYNCE
RESYNC
SYMBOL
POSITION NAME AND DESCRIPTION
RSMF
RCR1.7
RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6=1).
0=RSYNC outputs CAS multiframe boundaries
1=RSYNC outputs CRC4 multiframe boundaries
RSM
RSIO
RCR1.6
RCR1.5
RSYNC Mode Select.
0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)
RSYNC I/O Select. (Note: this bit must be set to 0 when
RCR2.1=0).
0=RSYNC is an output (depends on RCR1.6)
1=RSYNC is an input (only valid if elastic store enabled)
-
-
RCR1.4
RCR1.3
RCR1.2
Not Assigned. Should be set to 0 when written.
Not Assigned. Should be set to 0 when written.
FRC
Frame Resync Criteria.
0=resync if FAS received in error 3 consecutive times
1=resync if FAS or bit 2 of non-FAS is received in error 3
consecutive times
SYNCE
RCR1.1
RCR1.0
Sync Enable.
0=auto resync enabled
1=auto resync disabled
RESYNC
Resync. When toggled from low to high, a resync is initiated.
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