DS2152
14.1 RECEIVE CLOCK AND DATA RECOVERY
The DS2152 contains a digital clock recovery system. See the DS2152 Block Diagram in Section 1 and
Figure 14-1 for more details. The DS2152 couples to the receive T1 twisted pair via a 1:1 transformer.
See Table 14-3 for transformer details. The 1.544 MHz clock attached at the MCLK pin is internally
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16 times oversampler which is used to recover the clock and
data. This oversampling technique offers outstanding jitter tolerance (see Figure 14-2).
Normally, the clock that is output at the RCLKO pin is the recovered clock from the T1 AMI/B8ZS
waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,
a Receive Carrier Loss (LRCL) condition will occur and the RCLKO will be sourced from the clock
applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-
sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case
in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see
the Receive AC Timing Characteristics in Section 16 for more details.
14.2 TRANSMIT WAVESHAPING AND LINE DRIVING
The DS2152 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the
DS2152 meet the latest ANSI, AT&T, and ITU specifications. See Figure 14-3. The user will select
which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface
Control Register (LICR). The DS2152 can set up in a number of various configurations depending on the
application. See Table 14-2 and Figure 14-1.
LINE BUILD OUT SELECT IN LICR Table 14-2
L2
0
L1
0
L0
0
LINE BUILD OUT
0 to 133 feet / 0dB
133 to 266 feet
266 to 399 feet
399 to 533 feet
533 to 655 feet
-7.5 dB
APPLICATION
DSX-1 / CSU
DSX-1
0
0
1
0
1
0
DSX-1
DSX-1
DSX-1
CSU
0
1
1
1
0
0
1
0
1
1
1
0
-15 dB
CSU
1
1
1
-22.5 dB
CSU
Due to the nature of the design of the transmitter in the DS2152, very little jitter (less then 0.005 UIpp
broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLKI. Also, the waveforms that they
create are independent of the duty cycle of TCLK. The transmitter in the DS2152 couples to the T1
transmit twisted pair via a 1:1.15 or 1:1.36 step up transformer as shown in Figure 14-1. In order for the
devices to create the proper waveforms, this transformer used must meet the specifications listed in Table
14-3.
71 of 93
DALLAS [ DALLAS SEMICONDUCTOR ]
