DS2152
RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address=29 Hex)
RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address=2A Hex)
(MSB)
(LSB)
RFDL0
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
SYMBOL
POSITION NAME AND DESCRIPTION
RFDL7
RFDL0
RFDL.7
RFDL.0
MSB of the FDL Match Code
LSB of the FDL Match Code
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RFDLM1/RFDLM2), RSR2.2 will be set to a 1 and the INT will go active if enabled via IMR2.2.
11.2.3 Transmit Section
The transmit section will shift out into the T1 data stream either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full 8 bits have been shifted out, the DS2152 will signal the host microcontroller
that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The INT will also
toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the TFDL
is not updated, the old value in the TFDL will be transmitted once again.
The DS2152 also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2152 will
automatically look for five 1s in a row. If it finds such a pattern, it will automatically insert a 0 after the
five 1s. The CCR2.0 bit should always be set to a 1 when the DS2152 is inserting the FDL. More on how
to use the DS2152 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address=7E Hex)
[also used to insert Fs framing pattern in D4 framing mode; see Section 11.3]
(MSB)
(LSB)
TFDL7
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
TFDL0
SYMBOL
POSITION NAME AND DESCRIPTION
TFDL7
TFDL0
TFDL.7
TFDL.0
MSB of the FDL code to be transmitted
LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
11.3 D4/SLC-96 OPERATION
In the D4 framing mode, the DS2152 uses the TFDL register to insert the Fs framing pattern. To allow
the device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be
programmed to 1Ch and the following bits must be programmed as shown:
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DALLAS [ DALLAS SEMICONDUCTOR ]
