DS2152
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB)
(LSB)
LIRST
RLB
-
-
-
-
-
-
SYMBOL
POSITION NAME AND DESCRIPTION
LIRST
RLB
CCR7.7
CCR7.6
Line Interface reset. Setting this bit from a 0 to a 1 will initiate
an internal reset that affects the clock recovery state machine and
jitter attenuator. Normally this bit is only toggled on power-up.
Must be cleared and set again for a subsequent reset.
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
-
-
-
-
-
-
CCR7.5
CCR7.4
CCR7.3
CCR7.2
CCR7.1
CCR7.0
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Not Assigned. Should be set to 0 when written to.
Power-Up Sequence
On power-up, after the supplies are stable, the DS2152 should be configured for operation by writing to
all of the internal registers (this includes setting the Test Registers to 00Hex) since the contents of the
internal registers cannot be predicted on power-up. Finally, after the TSYSCLK and RSYSCLK inputs
are stable, the ESR bit should be toggled from a 0 to a 1 (this step can be skipped if the elastic stores are
disabled).
Remote Loopback
When CCR7.6 is set to a 1, the DS2152 will be forced into Remote LoopBack (RLB). In this loopback,
data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data
will continue to pass through the receive side framer of the DS2152 as it would normally and the data
from the transmit side formatter will be ignored. Please see Figure 1-1 for more details.
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DALLAS [ DALLAS SEMICONDUCTOR ]
