DS2152
RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex)
(MSB)
(LSB)
RL1
RL0
JALT
LORC
FRCL
-
-
-
SYMBOL
POSITION NAME AND DESCRIPTION
RL1
RL0
RIR3.7
RIR3.6
RIR3.5
Receive Level Bit 1. See Table 4-1.
Receive Level Bit 0. See Table 4-1.
JALT
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
LORC
FRCL
RIR3.4
RIR3.3
Loss of Receive Clock. Set when the RCLKI pin has not
transitioned for at least 2 us (3 us ± 1 us).
Framer Receive Carrier Loss. Set when 192 consecutive 0s
have been received at the RPOSI and RNEGI pins; allowed to be
cleared when 14 or more 1s out of 112 possible bit positions are
received.
-
-
-
RIR3.2
RIR3.1
RIR3.0
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
DS2152 RECEIVE T1 LEVEL INDICATION Table 4-1
RL1
RL0
TYPICAL LEVEL RECEIVED
+2 dB to -7.5 db
0
0
1
1
0
1
0
1
-7.5 dB to -15 db
-15 dB to -22.5 db
less than -22.5 db
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DALLAS [ DALLAS SEMICONDUCTOR ]
