DS18B20X
Therefore, the master must release the bus and then sample the bus state within 15 µs from the start of the
slot.
Figure 15 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15 µs for a read time slot.
Figure 16 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by locating the master sample time during read time slots towards the end of the 15 µs period.
DETAILED MASTER READ 1 TIMING Figure 15
VPU
VIH of Master
1-WIRE BUS
GND
TINT > 1 µs
TRC
Master samples
15 µs
RECOMMENDED MASTER READ 1 TIMING Figure 16
VPU
VIH of Master
1-WIRE BUS
GND
Master samples
TINT
= TRC =
small small
15 µs
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
RELATED APPLICATION NOTES
The following Application Notes can be applied to the DS18B20X. These notes can be obtained from the
Dallas Semiconductor “Application Note Book,” via the Dallas website at http://www.dalsemi.com/, or
through our faxback service at (214) 450–0441.
Application Note 27: “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor
Touch Memory Product”
Application Note 55: “Extending the Contact Range of Touch Memories”
Application Note 74: “Reading and Writing Touch Memories via Serial Interfaces”
Application Note 104: “Minimalist Temperature Control Demo”
Application Note 106: “Complex MicroLANs”
Application Note 108: “MicroLAN – In the Long Run”
Sample 1-wire subroutines that can be used in conjunction with AN74 can be downloaded from the
Dallas website or anonymous FTP Site.
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