16
8Bit Single Chip Microcontroller
DMC73C168
4.7.1 Peripheral Files detail Description
1)
I/O CONTROL REGISTERS
PF NAME
:
IOCTL0
:
I/O CONTROL REGISTER 0
BIT 6 BIT 5 BIT 4 BIT 3
R/W
READ
WRITE
BIT 7
NOT USED
BIT 2
BIT 1
BIT 0
INT3F INT3E INT2F INT2E INT1F INT1E
INT3C INT3E INT2C INT2E INT1C INT1E
P0
>0100
RESET VALUE
X
X
O
O
O
O
O
O
X = Indeterminate
Read
:
INTnF : 0 = INTn inactive
1 = INTn pending
Write : INTnE :0 = INTn disable
1 = INTn enable
INTnC :0 = No Effect
1 = Clear INTn flag
PF NAME
:
IOCTL1
:
I/O CONTROL REGISTER 1
BIT 6 BIT 5 BIT 4 BIT 3
R/W
READ
WRITE
BIT 7
BIT 2
INT40S
INT40S
O
BIT 1
BIT 0
INT1S
INT1S
O
INT41F INT41E INT40F INT40E
INT41C INT41E INT40C INT40E
INT3S
INT3S
O
P1
>0101
NOT
USED
O
O
O
O
X
RESET VALUE
X = Indeterminate
INT41 = INT4-1
INT40 = INT4-0
Read
:
INTnF : 0 = INTn inactive
1 = INTn pending
Write : INTnE :0 = INTn disable
1 = INTn enable
INTnS : 0 = Falling edge sensing
1 = Rising edgi sensing
INTnC :0 = No Effect
1 = Clear INTn flag
PF NAME
:
IOCTL2
:
I/O CONTROL REGISTER 2
BIT 6 BIT 5 BIT 4 BIT 3
R/W
READ
WRITE
BIT 7
BIT 2
BIT 1
BIT 0
P2
>0102
INT7F INT7E INT6F INT6E INT5F INT5E INT4F INT4E
INT7C INT7E INT6C INT6E INT5C INT5E
X
INT4E
O
RESET VALUE
O
O
O
O
O
O
O
Read
:
INTnF : 0 = INTn inactive
1 = INTn pending
Write : INTnE :0 = INTn disable
1 = INTn enable
This bit is automatically cleared
INTnC :0 = No Effect
When CPU fetch its vector address.
<< INT4F is not automatically cleared
When CPU fetch vector address>>
1 = Clear INTn flag
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