14
8Bit Single Chip Microcontroller
DMC73C168
order for any of the individual interrupts (INTn) to be recognized by the CPU. The Interrupt Enable
(I) bit can cleared by DINT instruction of by executing a device RESET (see Section 4.7).
4.6 Program Counter (PC)
’
The DMC73C168 s 16-bit Program Counter (PC) consists of two 8-bit registers in the CPU which
contain the MSB and the LSB respectively of a 16-bit address ; the Program Counter High (PCH) and
Low (PCL). The PC acts as the 16-bit address pointer of the opcodes and operands in memory of the
currently executing instruction. Upon assertion of the RESET function, the MSB and the LSB of the PC
are loaded into the A and B registers of the Register File (see Section 4.7).
4.7 Peripheral File Map
’
The Peripheral File (PF) resides in locations >0100 to >01BF of the DMC73C168 s address space as
shown in Table 4.7
Table 4.7 Peripheral File Map
RESET
REGISTER ADDRESS
NAME
IOCTL0
NOTE
FUNCTION
VALUE
00000000
0000x000
00000000
xxxxxxxx
P0
P1
P2
P4
>0100
>0101
>0102
>0104
1
1
1
1
Interrupt 1,2 and 3 control register
Ext-INT 1,3 and 4 input edge select
Interrupt 4,5,6,7 control register
Timer 1 MSB reload register
/ MSB readout latch
IOCTL1
IOCTL2
T1MSDATA
P5
P6
>0105
>0106
>0117
>0118
>0109
>010A
>010B
T1LSDATA
T1CTL0
1
1
1
1
1
1
1
Timer 1 LSB reload register
/ LSB decrementer value
Timer 1 control register 0
/ MSB readout latch
xxxxxxxx
x0xxxxxx
0x0xxxxx
xxxxxxxx
xxxxxxxx
00xxxxxx
0x0xxxxx
P7
T1CTL1
Timer 1 control register 1
/ LSB capture latch value
Timer 2 MSB reload register
/ MSB readout latch
P8
T2MSDATA
T2LSDATA
T2CTL0
P9
Timer 2 LSB reload register
/ LSB decrementer value
Timer 2 control register 0
/ MSB readout latch
P10
P11
T2CTL1
Timer 2 control register 1
/ LSB capture latch value
A port select control register
A/D converter control register
A/D converter data value
PLL control register 0
P13
P14
P15
P16
>010D
>010E
>010F
>0110
APSLCT
ADCTL
00000000
00xxxxx0
00000000
00000000
1
1
ADDATA
PLLCTL0
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