DMM Analog front end/Insulation
AC electrical characteristics
Parameter
SCLK clock frequency
SCLK clock time “L”
SLCK clock time “H”
SDATA output delay time
SDATA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCLK/SDATA rising time
SCLK/SDATA falling time
Bus release time
EOC setup time in read mode
EOC hold time in read mode
Symbol
f
SCLK
t
LOW
t
HIGH
t
AA
t
DH
t
SU.STA
t
HD.STA
t
SU.DAT
t
HD.DAT
t
SU.STO
t
R
t
F
t
BUF
t
SU.EOC
t
HD.EOC
Min.
-
4.7
4.0
0.1
100
4.7
4.0
200
0
4.7
-
-
4.7
0
0
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
100
-
-
3.5
-
-
-
-
-
-
1.0
0.3
-
-
Unit
kHz
us
ns
us
ns
us
ns
ns
ES51998(60000counts)
MPU I/O timing diagram
SCLK
SDATA IN
SDATA OUT
ver. 1.7
7
12/01/12
CYRUSTEK [ Cyrustek corporation ]
