USE ULTRA37000™ FOR
ALL NEW DESIGNS
Functional Logic Diagram for PALCE16V8
PIN NUMBERS
PRODUCT LINE FIRST CELL NUMBERS
0
00
64
128
192
3
4
7 8
11 12
15 16
19 20
23 24
27 28
31
INPUT LINE
NUMBERS
PIN NUMBERS
PALCE16V8
V
CC
1
20
MC7
CL1=2048
CL0=2120
PTD=2128
-2135
MC6
CL1=2049
CL0=2121
PTD=2136
-2143
MC5
CL1=2050
CL0=2122
PTD=2144
-2151
MC4
CL1=2051
CL0=2123
PTD=2152
-2159
MC3
CL1=2052
CL0=2124
PTD=2160
-2167
MC2
CL1=2053
CL0=2125
PTD=2168
-2175
MC1
CL1=2054
CL0=2126
PTD=2176
-2183
MC0
CL1=2055
CL0=2127
PTD=2184
-2191
32
96
160
224
19
2
256
320
384
448
288
352
416
480
18
3
512
576
640
704
544
608
672
736
17
4
768
832
896
960
800
864
928
992
16
5
1024
1088
1152
1216
1056
1120
1184
1248
15
6
1280
1344
1408
1312
1376
1504
14
14721440
7
1536
1600
1664
1568
1632
1760
13
17281696
8
1792
1856
1920
1824
1888
12
19841952
2016
9
10
0
3 4
2056
BYTE 0
7 8
2064
11 12 15 16 19 20 23 24 27 28
31
USER ELECTRONIC SIGNATURE ROW
2072
2080
2088
2096
2104
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
11
2112
2119
GLOBAL ARCH BITS
CG
0
=2192
CG
1
=2193
BYTE 1
BYTE 7
MSB LSB
MSB
LSB
Document #: 38-03025 Rev. *A
Page 8 of 13
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