PSoC® 3: CY8C32 Family
Data Sheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym Description
PHUB
Table 14-1. Acronyms Used in this Document (continued)
Acronym
SOF
Description
peripheral hub
physical layer
start of frame
PHY
PICU
PLA
SPI
Serial Peripheral Interface, a communications
protocol
port interrupt control unit
programmable logic array
programmable logic device, see also PAL
phase-locked loop
SR
slew rate
SRAM
SRES
SWD
SWV
TD
static random access memory
software reset
PLD
PLL
serial wire debug, a test protocol
single-wire viewer
PMDD
POR
PRES
PRS
PS
package material declaration datasheet
power-on reset
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
precise power-on reset
THD
TIA
pseudo random sequence
port read data register
TRM
TTL
®
PSoC
PSRR
PWM
RAM
RISC
RMS
RTC
RTL
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
TX
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
random-access memory
reduced-instruction-set computing
root-mean-square
UDB
universal digital block
Universal Serial Bus
USB
real-time clock
USBIO
USB input/output, PSoC pins used to connect to
a USB port
register transfer language
remote transmission request
receive
RTR
RX
VDAC
WDT
voltage DAC, see also DAC, IDAC
watchdog timer
SAR
SC/CT
SCL
successive approximation register
switched capacitor/continuous time
WOL
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
crystal
WRES
XRES
XTAL
2
I C serial clock
2
SDA
S/H
I C serial data
sample and hold
15. Reference Documents
SINAD
SIO
signal to noise and distortion ratio
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 3 Registers TRM
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
Document Number: 001-56955 Rev. *J
Page 113 of 119
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