CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Table 9. 56-Pin Part Pinout (SSOP)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Input
OCD
OCD
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Power
I
I
I
I
I
I
XRES
HCLK
CCLK
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
Analog column mux input and column
output.
Analog column mux input and column
output.
Analog column mux input.
Supply voltage.
Active high external reset with internal
pull down.
OCD high-speed clock output.
OCD CPU clock output.
LEGEND:
A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the
PSoC Mixed-Signal Array Technical Reference Manual
for details.
Document Number: 38-12012 Rev. *M
Page 15 of 53
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