CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
3. Electrical Specifications
3.4.10
AC I
2
C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C
≤
T
A
≤
85°C, or 3.0V to 3.6V and -40°C
≤
T
A
≤
85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-28. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd
Standard Mode
Symbol
Description
Min
Max
Fast Mode
Min
Max
Units
Notes
F
SCLI2C
T
HDSTAI2C
T
LOWI2C
T
HIGHI2C
T
SUSTAI2C
T
HDDATI2C
T
SUDATI2C
T
SUSTOI2C
T
BUFI2C
T
SPI2C
SCL Clock Frequency
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
0
4.0
4.7
4.0
4.7
0
250
4.0
4.7
–
100
–
–
–
–
–
–
–
–
–
0
0.6
1.3
0.6
0.6
0
100
a
0.6
1.3
0
400
–
–
–
–
–
–
–
–
50
kHz
µ
s
µ
s
µ
s
µ
s
µ
s
ns
µ
s
µ
s
ns
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
SU;DAT
≥
250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Figure 3-6. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
SDA
T
LOWI2C
T
SUDATI2C
T
HDSTAI2C
T
SPI2C
T
BUFI2C
SCL
S
T
HDSTAI2C
T
HDDATI2C
T
HIGHI2C
T
SUSTAI2C
Sr
T
SUSTOI2C
P
S
February 15, 2007
Document No. 38-12018 Rev. *J
38
CYPRESS [ CYPRESS SEMICONDUCTOR ]
