CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Pin Descriptions
The following table lists the pinouts for the 56-pin SSOP, 56-pin QFN, and 100-pin TQFP package options for the AT2LP. Refer to the
on the CY7C68300A pinout, refer to the CY7C68300A data sheet that is found in the ’EZ-USB AT2’ folder of the
CY4615C reference
design kit CD.
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)
100
TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
56
QFN
55
56
1
2
N/A
56
SSOP
6
7
8
9
N/A
Pin Name
V
CC
GND
IORDY
DMARQ
GND
Pin Default State
Type
at Startup
PWR
GND
Input
Input
Ground.
Pin Description
V
CC
. Connect to 3.3V power source.
ATA control.
Apply a 1k pull up to 3.3V.
ATA control.
Ground.
3
4
5
6
N/A
10
11
12
13
N/A
AV
CC
XTALOUT
XTALIN
AGND
NC
PWR
Xtal
Xtal
GND
Xtal
Xtal
Analog V
CC
. Connect to V
CC
through the shortest path
possible.
24 MHz crystal output.
(See
24 MHz crystal input.
(See
Analog ground.
Connect to ground with as short a
path as possible.
No connect.
7
8
9
10
11
12
N/A
14
15
16
17
18
19
N/A
V
CC
DPLUS
DMINUS
GND
V
CC
GND
SYSIRQ
PWR
I/O
I/O
GND
PWR
GND
I
Input
Hi-Z
Hi-Z
V
CC
. Connect to 3.3V power source.
USB D+ signal
(See
USB D–signal
(See
Ground.
V
CC
. Connect to 3.3V power source.
Ground.
USB interrupt request.
(See
Active HIGH. Connect to GND if functionality is not
used.
Ground.
23
24
25
26
N/A
N/A
GND
GND
13
20
PWR500#
(PU
10K)
GND (RESERVED)
O
bMaxPower request granted indicator.
(See
N/A for CY7C68320C/CY7C68321C 56-pin packages.
Reserved.
Tie to GND.
27
14
21
Notes
1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See
2. A ‘#’ sign after the pin name indicates that it is active LOW.
3. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C.
Document 001-05809 Rev. *C
Page 9 of 41
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