CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)
(continued)
100
TQFP
94
95
96
97
98
99
100
56
QFN
N/A
49
50
51
52
53
54
56
SSOP
N/A
56
1
2
3
4
5
Pin Name
GND
DD12
DD13
DD14
DD15
GND
ATAPUEN
(NC)
Pin Default State
Type
at Startup
GND
I/O
I/O
I/O
Pin Description
Ground.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ATA data bit 12.
ATA data bit 13.
ATA data bit 14.
ATA data bit 15.
Ground.
Bus-powered ATA pull up voltage source
(see
Alternate function:
General purpose input when the
EEPROM configuration byte 8 has bit 7 set to ‘1’. The
input value is reported through EP1IN (byte 0, bit 2).
I/O
GND
I/O
Additional Pin Descriptions
The following sections provide additional pin information.
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins; they must
be tied to the D+ and D– pins of the USB connector. Because
they operate at high frequencies, the USB signals require
special consideration when designing the layout of the PCB.
See
tions.
When RESET# is released, the assertion of the internal pull
up on D+ is gated by a combination of the state of the
VBUS_ATA_ENABLE pin, the value of configuration address
0x08 bit 0 (DRVPWRVLD Enable), and the detection of a
non-removable ATA/ATAPI drive on the IDE bus. See
for a description of this relationship.
Table 2. D+ Pull Up Assertion Dependencies
VBUS_ATA_EN
DRVPWRVLD Enable Bit
ATA/ATAPI Drive Detected
State of D+ pull up
SCL, SDA
The clock and data pins for the I
2
C port must be connected to
the configuration EEPROM and to 2.2K pull up resistors tied
to V
CC
. If no EEPROM is used in the design, the SCL and SDA
pins must still be connected to pull up resistors. The SCL and
SDA pins are active for several milliseconds at startup.
1
1
Yes
XTALIN, XTALOUT
The AT2LP requires a 24 MHz (
±
100 ppm) signal to derive
internal timing. Typically, a 24 MHz (12 pF, 500
μW,
parallel-resonant, fundamental mode) crystal is used, but a
24 MHz square wave (3.3V, 50/50 duty cycle) from another
source can also be used. If a crystal is used, connect its pins
to XTALIN and XTALOUT, and also through 12 pF capacitors
to GND as shown in
If an alternate clock source is
used, apply it to XTALIN and leave XTALOUT unconnected.
Figure 7. XTALIN/XTALOUT Diagram
24MHz Xtal
12pF
12pF
1
1
No
1
0
Yes
1
0
No
0
1
Yes
0
1
No
1
1
1
0
0
0
XTALIN
XTALOUT
Document 001-05809 Rev. *C
Page 12 of 41
CYPRESS [ CYPRESS SEMICONDUCTOR ]
