CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.17 Sequence Diagram
10.17.1 Single and Burst Synchronous Read Example
Figure 29. Slave FIFO Synchronous Read Sequence and Timing Diagram[20]
t
IFCLK
IFCLK
t
t
SFA
SFA
t
t
FAH
FAH
FIFOADR
t=0
T=0
t
t
>= t
SRD
>= t
RDH
RDH
SRD
SLRD
SLCS
t=3
t=2
T=3
T=2
t
XFLG
FLAGS
DATA
SLOE
t
t
t
XFD
t
XFD
XFD
XFD
N+4
Data Driven: N
N+2
N+3
N+1
N+1
t
t
t
OEoff
OEon
t
OEoff
OEon
t=4
T=4
T=1
t=1
Figure 30. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
IFCLK
N
IFCLK
N+1
IFCLK
N+1
IFCLK
N+1
IFCLK
N+2
IFCLK
N+3
IFCLK
N+4
IFCLK
N+4
IFCLK
N+4
N
FIFO POINTER
SLOE
SLRD
SLOE
SLRD
SLOE
SLRD
SLRD
SLOE
FIFO DATA BUS Not Driven
Driven: N
N+1
Not Driven
N+1
N+2
N+3
N+4
N+4
Not Driven
Figure 29 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
If the SLCS signal is used, it must be asserted before SLRD is
asserted (The SLCS and SLRD signals must both be asserted
to start a valid read condition).
■
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge of
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
MUST also be asserted.
■
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications). Note
that tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■
At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO. Note: the data is pre-fetched and is driven on the bus
when SLOE is asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle, on the rising edge of the
clock the FIFO pointer is updated and increments to point to
address N+1. For each subsequent rising edge of IFCLK, while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
■
At t = 2, SLRD is asserted. SLRD must meet the setup time of
tSRD (time from asserting the SLRD signal to the rising edge of
the IFCLK) and maintain a minimum hold time of tRDH (time
from the IFCLK edge to the deassertion of the SLRD signal).
Document #: 38-08032 Rev. *N
Page 50 of 62
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