CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.10 Slave FIFO Asynchronous Write
Figure 21. Slave FIFO Asynchronous Write Timing Diagram[20]
t
WRpwh
SLWR
SLWR/SLCS#
t
WRpwl
t
t
FDH
SFD
DATA
t
XFD
FLAGS
Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [23]
Parameter
tWRpwl
tWRpwh
tSFD
Description
Min
50
Max
Unit
ns
SLWR Pulse LOW
SLWR Pulse HIGH
70
ns
SLWR to FIFO DATA Setup Time
FIFO DATA to SLWR Hold Time
10
ns
tFDH
10
ns
tXFD
SLWR to FLAGS Output Propagation Delay
70
ns
10.11 Slave FIFO Synchronous Packet End Strobe
Figure 22. Slave FIFO Synchronous Packet End Strobe Timing Diagram[20]
IFCLK
t
PEH
PKTEND
FLAGS
t
SPE
t
XFLG
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min
20.83
14.6
0
Max
Unit
ns
IFCLK Period
tSPE
tPEH
tXFLG
PKTEND to Clock Setup Time
ns
Clock to PKTEND Hold Time
ns
Clock to FLAGS Output Propagation Delay
9.5
ns
Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min
20.83
8.6
Max
Unit
ns
IFCLK Period
200
tSPE
tPEH
tXFLG
PKTEND to Clock Setup Time
ns
Clock to PKTEND Hold Time
2.5
ns
Clock to FLAGS Output Propagation Delay
13.5
ns
Document #: 38-08032 Rev. *N
Page 46 of 62
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