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CY7C68014A-56LTXC 参数 Datasheet PDF下载

CY7C68014A-56LTXC图片预览
型号: CY7C68014A-56LTXC
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内容描述: EZ- USB FX2LP USB微控制器,高速USB外设控制器 [EZ-USB FX2LP USB Microcontroller High Speed USB Peripheral Controller]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 62 页 / 1626 K
品牌: CYPRESS [ CYPRESS ]
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CY7C68013A, CY7C68014A  
CY7C68015A, CY7C68016A  
10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write  
Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram[20]  
t
t
t
FAH  
t
SFA  
SFA  
FAH  
FIFOADR  
t=0  
T=0  
t
t
t
t
t
t
t
t
WRpwh  
WRpwl  
WRpwh  
WRpwl  
WRpwl  
WRpwh  
WRpwh  
WRpwl  
SLWR  
SLCS  
t =1  
t=3  
T=1  
T=4  
T=3  
T=7  
T=6  
T=9  
t
XFLG  
t
XFLG  
FLAGS  
DATA  
t
t
t
t
t
t
t
SFD  
t
SFD FDH  
SFD FDH  
SFD FDH  
FDH  
N
N+1  
N+2  
N+3  
t=2  
T=8  
T=2  
T=5  
t
t
PEpwl  
PEpwh  
PKTEND  
Figure 34 shows the timing relationship of the SLAVE FIFO write  
in an asynchronous mode. The diagram shows a single write  
followed by a burst write of 3 bytes and committing the 4 byte  
short packet using PKTEND.  
The FIFO flag is also updated after tXFLG from the deasserting  
edge of SLWR.  
The same sequence of events are shown for a burst write and is  
indicated by the timing marks of T = 0 through 5.  
At t = 0 the FIFO address is applied, insuring that it meets the  
setup time of tSFA. If SLCS is used, it must also be asserted  
(SLCS may be tied low in some applications).  
Note In the burst write mode, after SLWR is deasserted, the data  
is written to the FIFO and then the FIFO pointer is incremented  
to the next byte in the FIFO. The FIFO pointer is post  
incremented.  
At t = 1 SLWR is asserted. SLWR must meet the minimum  
active pulse of tWRpwl and minimum de-active pulse width of  
In Figure 34 after the four bytes are written to the FIFO and  
SLWR is deasserted, the short 4 byte packet can be committed  
to the host using the PKTEND. The external device should be  
designed to not assert SLWR and the PKTEND signal at the  
same time. It should be designed to assert the PKTEND after  
SLWR is deasserted and met the minimum deasserted pulse  
width. The FIFOADDR lines have to held constant during the  
PKTEND assertion.  
tWRpwh. If the SLCS is used, it must be asserted with SLWR or  
before SLWR is asserted.  
At t = 2, data must be present on the bus tSFD before the  
deasserting edge of SLWR.  
At t = 3, deasserting SLWR causes the data to be written from  
the data bus to the FIFO and then increments the FIFO pointer.  
Document #: 38-08032 Rev. *N  
Page 53 of 62  
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