CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.8 Slave FIFO Asynchronous Read
Figure 19. Slave FIFO Asynchronous Read Timing Diagram[20]
t
RDpwh
SLRD
t
RDpwl
t
XFLG
t
FLAGS
XFD
DATA
SLOE
N+1
N
t
t
OEoff
OEon
Table 22. Slave FIFO Asynchronous Read Parameters[23]
Parameter Description
tRDpwl SLRD Pulse Width LOW
SLRD Pulse Width HIGH
Min
Max
Unit
ns
50
50
tRDpwh
tXFLG
tXFD
ns
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
70
15
ns
ns
tOEon
tOEoff
10.5
10.5
ns
SLOE Turn-off to FIFO Data Hold
ns
Note
23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document #: 38-08032 Rev. *N
Page 44 of 62
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